I dug through some old fab docs to make these interesting graphs of transistor scaling. no cherry picking of data here - first up is process node + actual FET size, they& #39;ve been lying to us since the mid 90s but at least reality was better than marketing then! look at 2010...

since a "5nm" or "7nm" process is basically meaningless now, we can look at more useful metrics like the area of silicon it takes for 1 cell of SRAM. They got a little lost in the mid 70s but then it was a race to the bottom

And of course billions of transistors are useless unless you can wire them up.our brain is pretty good because it has a 3D volume available for that. chips only have a 2D area but many metal layers are stacked on modern chips. It took a while to break away from just 1 metal layer

the http://plt.style"> http://plt.style .use("dark_background") is the most important part here

Many people use an image similar to this as proof for moore& #39;s law being dead (the yellow line has stopped going down) but keep in mind there are many factors contributing to # of transistors on a chip, gate length was not responsible for any of the recent scaling